PN junction diodes have been used as a protection element for preventing semiconductor devices from being destroyed due to electrostatic discharge (ESD), a surge voltage, or a surge current. Such a PN junction diode for input/output protection is disclosed in Japanese patent application provisional publication No. 02-58262.
FIG. 22A is a plan view of a related art typical PN junction diode for input/output protection. FIG. 22B is an enlarged cross-sectional view taken along line XXIIB—XXIIB in FIG. 22A.
The PN junction diode 100 shown in FIGS. 22A and 22B includes an N-type low impurity concentration silicon semiconductor substrate (n−)1, a P-type high impurity concentration diffusion region 2 as a base in the surface portion of the substrate 1, and N-type high impurity concentration diffusion regions 3a and 3b as an emitter on both sides of the base in the surface layer of the substrate 1 to provide PN junction. In FIG. 22A, the P-type high impurity concentration diffusion region 2 and the N-type high impurity concentration diffusion regions 3a and 3b are denoted with broken lines.
As shown in FIG. 22B, the P-type high impurity diffusion region 2 and the N-type high impurity diffusion regions 3a and 3b are connected to Al electrodes 7a and 7b through openings in an insulation film 5 comprising BPSG (borophosphosilicate glass), respectively. More specifically, as shown in the plan view of FIG. 22A, the P-type high impurity concentration diffusion region 2 is connected to the Al electrode 7a as a base electrode, and the N-type high impurity concentration diffusion regions 3a and 3b are connected together with the Al electrode 7b as an emitter electrode. Here, in the plan view of FIG. 22A, the Al electrodes 7a and 7b are denoted with solid lines, and the contact regions 71, 72, and 73 are denoted with dotted lines. Further, the whole of the PN junction diode is covered with a protection film 10 comprising silicon nitride (SiN) and is connected to the external through pads 70a and 70b denoted with solid lines in FIG. 22A. Each of the high impurity concentration regions 2, 3a, and 3b has a rectangular shape having dimensions of about 10 ìm×500 ìm. The PN junction diode for input/output protection element for a semiconductor device has tens of PN junction diodes in FIGS. 22A and 22B connected in parallel to protect the circuits in the semiconductor device from a large magnitude of serge current.
Next, a method of producing the PN junction diode shown in FIGS. 22A and 22B will be described with reference to FIGS. 23A to 23E. FIGS. 23A to 23E are enlarged cross-sectional views taken along line XXIIB—XXIIB in FIG. 22A in order of production processes.
As shown in FIG. 23A, on an N-type low impurity concentration silicon (semiconductor) substrate 1, a first mask 101 corresponding to the base is formed, and then P-type impurity is ion-injected at a relatively high concentration to form the P-type high impurity concentration diffusion region 2 to provide the base.
Subsequently, as shown in FIG. 23B, the first mask 101 corresponding to the base is removed, and then a second mask 102 corresponding to the emitter is formed. Next, N-type impurity is ion-injected at a relatively high concentration to form N-type high impurity concentration diffusion regions 3a and 3b as the emitter on the both sides of the P-type high impurity concentration diffusion region 2. This provides PN junction regions 4a and 4b at the semiconductor portions between the P-type high impurity concentration diffusion region 2 and the N-type high impurity concentration diffusion regions 3a and 3b. 
Next, as shown in FIG. 23C, the second mask 102 corresponding to the emitter is removed, and then a BPSG film as an intermediate insulation film 5 is deposited on a entire surface of the substrate 1. Openings 61, 62 and 63 are formed to obtain connections with the P-type high impurity concentration diffusion region 2 and N-type high impurity concentration diffusion regions 3a and 3b, respectively.
After that, as shown in FIG. 23D, Al is deposited on the entire current top surface to have an Al film, which is patterned to have a base electrode 7a and emitter electrodes 7b. 
Now, as shown in FIG. 23E, SiN is deposited on the entire top surface to have a protection film 10, and then openings for pads are formed for external connection to complete the PN junction diode 100 shown in FIGS. 22A and 22B
When a surge such as ESD is applied to the N-type high diffusion regions 3a and 3b as the emitter, immediately, the PN junction regions 4a and 4b are reversely biased. This generates an avalanche conduction, so that a surge current flows from the N-type high impurity concentration diffusion regions 3a and 3b to the P-type high impurity concentration diffusion region 2. The PN junction regions 4a and 4b have widths Lca and Lcb, respectively, which are equal to each other in designing step. However, in the manufacturing step, the widths Lca and Lcb may become different from each other (in the figure, Lca<Lcb). In FIG. 22B, as shown by the arrows having different thicknesses, a surge current flowing through the PN junction region 4a having a smaller width is greater in magnitude than the surge current flowing through the PN junction region 4b. Thus, the diode having deviation in a magnitude of a surge current due to the different widths Lca and Lcb, has a relatively low withstanding voltage against a surge voltage, thus, being easily destroyed.
Moreover, particularly, the P-type high impurity concentration diffusion region 2 and the N-type high impurity concentration diffusion regions 3a and 3b having rectangular edges may be subjected to destruction due to a surge voltage because electric surge current concentrates thereto.
Therefore, it would be desirable to provide a PN junction diode capable of suppressing the concentration of electric surge current at the ends of the stripe diffusion regions therein.
Further, it would be also desirable to provide a PN junction diode in which the surge currents can be uniformly conducted through each of plural PN junction regions.